#ifndef CE478_H
#define CE478_H

/* ===========================================================================

	ce478.h	

	Version:		1

==============================================================================

NOTES:

	For 40mhz operation, the PLPRCR register is loaded with 0x90 0000

JUMPERS:
	EXT-EN	ON = Board boots at CS0 Address offset 0x100
			OFF = Board boots from internal flash absolute address 0x100

	EXT-CFG	Does nothing if EXT-EN jumper is OFF
			Otherwise Hard Reset controled by Mode switch banks 1 & 2

	External Chip Selects:

		1 = CS0
		2 = CS1
		3 = CS2
			CS3 is used by Keypad/LCD peripherals

		RAM-SEL		Sets the External RAM chip select
		FLSH-SEL    Sets the External Flash chip select
		M-SEL		Sets the External EPROM chip select


------------------------------------------------------------------------------
 MEMORY MAP

0x0000 0000		CMF Internal Flash Array - CDR MoneT Flash EEPROM
0x0006 FFFF

0x0007 0000		Reserved by internal memory block
0x002F BFFF

0x002F C000		USIU - Control Registers
0x002F C3FC

0x002F C800     CMF - Control Registers
0x002F C848

0x0030 0000     DPTRAM - Control Registers
0x0030 000A

0x0030 2000		DPTRAM Dual Port TPU RAM Array
0x0030 37FF

0x0030 4000		TPU3 Time Processor Unit - Registers
0x0030 45FF

0x0030 4800		QADC64 Queued A/D Converter - Registers
0x0030 4FFF

0x0030 5000		QSMCM Queued Serial - Registers
0x0030 51DF

0x0030 6000		MIOS1 Modular I/O Subsystem - Registers
0x0030 6C70

0x0030 7080		TouCAN - Registers
0x0030 74A6

0x0030 7F80		UIMB U-Bus to IMB3 Bus Interface- Registers
0x0030 7FA0


0x0038 0000		Internal SRAM - Control Registers
0x0038 000C


0x003F 8000		Reserved
0x003F 97FF

0x003F 9800		Internal SRAM Array
0x003F FFFF


----------  default memory assigned by monitor --------------

0x0040 0000		External EEPROM (monitor)			----- CS0
0x007F FFFF

0x0080 0000		External RAM Array					----- CS1
0x00BF FFFF

0x00C0 0000		External Flash Array 				----- CS2
0x00FF FFFF

0x0100 0000		Peripheral Devices (keypad/LCD)		----- CS3
0x013F FFFF

0x0140 0000		unmapped address space
0xFFFF FFFF

------------------------------------------------------------------------------
*/

/*-------------------
Constant Definitions
--------------------*/
//#define EFLASH_ADDR	0xC00000		// this is where the external flash memory starts  - Realtime mode from EEPROM
//#define EFLASH_ADDR	0x400000		// this is where the external flash memory starts  - Realtime mode from onboard flash
//#define EFLASH_ADDR	0x800000		// this is where the external flash memory starts  - BDM / programming mode

#define	INBUFSIZE	255		// size in bytes of the serial input buffer


#define LF 10			/* line feed */
#define CR 13			/* carriage return */
#define TRUE 1
#define FALSE 0
#define HWORD short
#define WORD long

#define TARGET_RAM		0
#define TARGET_EFLASH	1
#define TARGET_IFLASH	2
#define TARGET_EFLASH_O	3


/*------------
I/O Registers
------------*/
short Com1Con0:0x305008;	// SCI1 control register 0
short Com1Con1:0x30500A;	// SCI1 control register 1
short Com1Status:0x30500C;	// SCI1 status register
short Com1Data:0x30500E;	// SCI1 data register

short Com2Con0:0x305020;	// SCI2 control register 0
short Com2Con1:0x305022;	// SCI2 control register 1
short Com2Status:0x305024;	// SCI2 status register
short Com2Data:0x305026;	// SCI2 data register

short MPIOSMDR:0x306100;	// MPIOSM data register
short MPIOSMDDR:0x306102;	// MPIOSM data direction register - 1 = output

short QADC1DR:0x304806;		// QADC 1 data register
short QADC1DDR:0x304808;	// QADC 1 data direction register (port A)
short QADC2DR:0x304C06;		// QADC 2 data register
short QADC2DDR:0x304C08;	// QADC 2 data direction register (port A)

short PORTQS:0x305014;		// QSM data register
short PQSPAR:0x305016;		// QSM data direction register

short WatchDog:0x2FC00E;	// SWSR software service register

//---------------------------------------------------------------------------
// INITIALIZE HARDWARE REGISTERS
// This routine is called once following RESET
void inithw();
void inithw(){
	unsigned long *Rptr;


	Rptr = (unsigned long *) 0x2fc000;	// SIUMCR
	*Rptr = 0x00;
	Rptr = (unsigned long *) 0x2fc004;	// SYPCR
	*Rptr = 0xFF88;

	Rptr = (unsigned long *) 0x2fc100;	// BR0
	*Rptr = 0x400003;	// 32-bit set here for BDM or external flash
	Rptr = (unsigned long *) 0x2fc104;	// OR0
	*Rptr = 0xfff80012;

	Rptr = (unsigned long *) 0x2fc118;	// BR3
	*Rptr = 0x01000403;	// works for Keypad/LCD
	Rptr = (unsigned long *) 0x2fc11c;	// OR3
	*Rptr = 0xfffe0FF1;	// maximum wait states

}


// reset / clear the watchdog
void ClearWatchdog();
void ClearWatchdog(){
	WatchDog = (unsigned short)0x556C;	// clear the watchdog
	WatchDog = (unsigned short)0xAA39;
}

// delay the specified number of milliseconds using the pit timer
void delay(unsigned int);
void delay(unsigned int dtime){
	unsigned long pval;
	//unsigned long nval;
	unsigned int dloop;

	dloop = dtime * 2;	// calculate 1 ms time
	if(dtime > 2){
		dloop += (dtime / 2);	// add fraction
	}
	if(dtime > 10){
		dloop += (dtime / 10);	// add fraction
	}

	while(dloop > 0){
		for(pval=0xFF; pval > 0; pval--){
			ClearWatchdog();	// feed the dog
		}
		--dloop;
	}
}

// send 1 byte to the specified port
void outportb(unsigned long, unsigned char);
void outportb(unsigned long portaddr, unsigned char chval){
	unsigned char *Rptr;

	Rptr = (unsigned char *) portaddr;
	*Rptr = chval;
}



#endif

